Design verification by symbolic simulation using a native hardware description language

ABSTRACT

A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of design simulationand verification; more particularly, the present invention relates toaugmenting design descriptions to perform design verification bysymbolic simulation.

BACKGROUND OF THE INVENTION

[0002] The sophistication of modem integrated circuit (IC) design meansthat designers have to rely on automation tools (ICDA) to manage thecomplexity. Over the past two decades, new tools have continually beendeveloped to increase the level of automation and enable designers todevelop increasingly complex and powerful IC products.

[0003] The increasing demand for new IC design tools is fueled byrapidly changing IC fabrication process technology. As IC feature sizesshrink to dimensions of 0.25 micron and smaller, the complexity of thedesigns (number of devices on a single chip) drives the need forimproved techniques to design and verify the required functionality.

[0004] The continuing increase in IC design complexity, along with thelack of specific automation tools, has led to design verificationbecoming a major design bottleneck.

[0005] There are a number of alternatives currently being used to reducethe verification bottleneck. These include both dynamic and staticverification. Dynamic verification is the standard approach toverification. Recent advances in dynamic verification can be categorizedinto two categories: testbench management and augmented verificationtechniques.

[0006] Testbench management tools abstract the creation of test vectorsto a higher level. These tools provide a language to help an individualcreate tests and measurement tools to help the individual quantify howgood coverage is. Testbench management has a number of advantages thatinclude providing an evolutionary step to the problem of designverification, automating many of the repetitive tasks and helps thedesigner focus on the problem of what to test, and providing a way ofreducing the ambiguity of the test specification. Testbench managementprovides a number of disadvantages which include being based on thecontinued use of digital or binary simulation and large numbers of testvectors, forcing a designer to use a proprietary test language toexpress tests, and having non-simplified debugging.

[0007] Augmented verification techniques can be used with existingapproaches and testbench management tools. Testbench management toolsprovide some augmented verification techniques, but these augmentedtechniques seek to improve measurement and increase test coverage. Theuse of augmented verification techniques is advantageous in that itprovides an evolutionary step to the problem of design verification,improves the observability of the tests, and automates some of the stepsof test creation to improve the scope of testing. The disadvantages ofaugmented verification techniques include being based on the use ofbinary simulation and large numbers of vectors, forcing a designer touse a proprietary methodology, and having no guarantee that the testswill catch all problems.

[0008] Static verification is a new technology that attempts to formallyprove that a design meets its specifications.

[0009] Other verification techniques include equivalence checking whichcompares two gate level netlists is fairly established and its benefitsare not an issue. However, application of the same formal techniques tocompare RTL or behavior against a specification is still problematic.Model checking (behavior/RTL−RTL/gate checking) is still in the veryearly stages of use. Its inherent limitation of a maximum of about 200registers means that model checking has very limited use withoutextensive engineering effort.

[0010] The advantages of this approach include providing exhaustive andconclusive proof that the design is correct, managing non-linear growthin design size, and providing rapid response and precise debugging. Thedisadvantages of this approach include having technical limitations suchthat it is only appropriate for a very small number of designs, veryhard for engineers to grasp, and demands substantial reworking of designcapture techniques.

[0011] Both dynamic and static approaches have merit; however, there isan immediate problem that neither approach can solve today. Until now,there has been no adequate solution to the growing crisis of designverification. Existing simulation techniques are not able to keep upwith complexity growth. Formal techniques have too many restrictions andfunctional verification is the major cause of problems in a designproject. Therefore, a need exists to provide an improved simulationtechnique that reduces the number of restrictions that currently existin a design project.

SUMMARY OF THE INVENTION

[0012] A method and apparatus for performing design verification isdescribed. In one embodiment, a method for performing designverification includes specifying at least one object that represents atleast one signal as a symbol in a design using a first programminginterface call and instructing a symbolic simulator with the firstprogramming interface call to treat the at least one object as a symbol.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the invention, which, however, should not betaken to limit the invention to the specific embodiments, but are forexplanation and understanding only.

[0014]FIG. 1 is a flow diagram of one embodiment of a process forverifying a design.

[0015]FIG. 2 is a block diagram of a circuit showing symbolic simulationpropagating symbols in logic expressions.

[0016]FIG. 3 is an exemplary arithmetic logic unit.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0017] A method and apparatus for improved design verification isdescribed. In the following description, numerous details are set forth.It will be apparent, however, to one skilled in the art, that thepresent invention may be practiced without these specific details. Inother instances, well-known structures and devices are shown in blockdiagram form, rather than in detail, in order to avoid obscuring thepresent invention.

[0018] Some portions of the detailed descriptions that follow arepresented in terms of algorithms and symbolic representations ofoperations on data bits within a computer memory. These algorithmicdescriptions and representations are the means used by those skilled inthe data processing arts to most effectively convey the substance oftheir work to others skilled in the art. An algorithm is here, andgenerally, conceived to be a self-consistent sequence of steps leadingto a desired result. The steps are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, transferred, combined, compared, and otherwisemanipulated. It has proven convenient at times, principally for reasonsof common usage, to refer to these signals as bits, values, elements,symbols, characters, terms, numbers, or the like.

[0019] It should be borne in mind, however, that all of these andsimilar terms are to be associated with the appropriate physicalquantities and are merely convenient labels applied to these quantities.Unless specifically stated otherwise as apparent from the followingdiscussion, it is appreciated that throughout the description,discussions utilizing terms such as “processing” or “computing” or“calculating” or “determining” or “displaying” or the like, refer to theaction and processes of a computer system, or similar electroniccomputing device, that manipulates and transforms data represented asphysical (electronic) quantities within the computer system's registersand memories into other data similarly represented as physicalquantities within the computer system memories or registers or othersuch information storage, transmission or display devices.

[0020] The present invention also relates to apparatus for performingthe operations herein. This apparatus may be specially constructed forthe required purposes, or it may comprise a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program may be stored in a computerreadable storage medium, such as, but is not limited to, any type ofdisk including floppy disks, optical disks, CD-ROMs, andmagnetic-optical disks, read-only memories (ROMs), random accessmemories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any typeof media suitable for storing electronic instructions, and each coupledto a computer system bus.

[0021] The algorithms and displays presented herein are not inherentlyrelated to any particular computer or other apparatus. Various generalpurpose systems may be used with programs in accordance with theteachings herein, or it may prove convenient to construct morespecialized apparatus to perform the required method steps. The requiredstructure for a variety of these systems will appear from thedescription below. In addition, the present invention is not describedwith reference to any particular programming language. It will beappreciated that a variety of programming languages may be used toimplement the teachings of the invention as described herein.

[0022] Overview

[0023] The present invention allows hardware description languages thatare normally used to describe designs to be used in symbolic simulators.The present invention allows this instructing the symbolic simulator totreat one or more specified signals (e.g., inputs) as symbolic.

[0024] In one embodiment, the simulator is instructed through the use ofone or more programming commands, or statements, (e.g., programminginterface calls (PLIs)) that declare certain variables as symbols. Thatis, a command may be used to indicate to the simulator that an object ina hardware description language used to indicate a signal (e.g., aVerilog object) is to be a symbol to the simulator, such that variableassigned objects are designated as symbolic variable objects. In thismanner, the existing hardware description languages are able to supportthe specification of symbolic input. Upon encountering such aprogramming statement, the symbolic simulator propagates logicexpressions, instead of binary values, capturing the relationship frominput to output.

[0025] The present invention permits a check to be inserted to perform acomplete test and generate information allowing the re-creation of anyidentified fault. In one embodiment, the simulator is instructed toperform the check through the use of one or more programming statementsthat generate a file of one or more vectors (e.g., binary vectors) thatmay be used to locate any identified fault, thereby simplifying debug.Once an error has been identified, well-known simulators that employbinary numbers may be used to isolate the fault.

[0026] By using symbolic simulation, in one simulation run, manycombinations of binary simulation runs are achieved to verify thedesign, such that the simulator verifies the complete behavior of adesign in a more efficient manner than traditional simulation.

[0027] Design Verification Flow

[0028]FIG. 1 is a flow diagram of one embodiment of a process comprisinga series of processing steps to simulate a design. The process may beperformed by processing logic which may comprise software, hardware or acombination of both.

[0029] Referring to FIG. 1, the process augments a design to specify tothe simulator the signals to treat as symbolic (processing block 101).The signals may be inputs, interrupts, memory values, or any otherportion of a design that may be represented as an object in a hardwaredescription language.

[0030] In one embodiment, the input engine of the simulator accepts aVerilog netlist of a block and the users instructs the simulator to runwith one, more or all inputs symbolically. In such a case, the user mayspecify which inputs using a programming language interface (PLI)command which is inserted into the design flow. Other languages may haveother similar mechanisms to the PLIs, such as for example using an APIin HDL, and may be used in the same manner.

[0031] In one embodiment, the process instructs the simulator using thefollowing PLI command:

[0032] $esp_var(a, b, . . . )

[0033] which causes the simulator to designate the objects a, b, etc. assymbols. In one embodiment, any number of objects may be listed in thePLI command. A symbol database may be used to keep track of thedefinitions of each symbol.

[0034] Then, the process compiles the design description (processingblock 102). During compile, the symbolic variables are recognized, viathe PLIs, and an internal intermediary structure for the symbolicsimulator.

[0035] Next, the process performs symbolic simulation (processing block103). Symbolic simulation allows the designer to add symbols to existingbinary values (0, 1, X and Z) during simulation. When the simulatordetects symbol input, it propagates a boolean expression instead ofpropagating the digital value that is the result of the logicaloperation on the inputs. As the expressions are propagated, they capturethe input/output mapping for all possible conditions. Although the finaloutput expression may be very lengthy, they can readily be used to checkagainst specified assertions or to compare against a reference model,particularly where the reference model is in symbolic format as well. Byusing symbols, one is able to fully verify a block without having toselect a set of values. FIG. 2 illustrates an example of expressionsbeing propagated from the input to the output of a design.

[0036] While performing symbolic simulation, the simulator is instructedto make checks to validate the functionality of the design. In oneembodiment, another PLI command is inserted into the designspecification in order to instruct the simulator to detect faults. Ifthe design specification is in Verilog, one embodiment of the PLIcommand may be as follows:

[0037] $esp_error( )

[0038] which generates a file with the binary vector needed to locatethe fault (so that debugging is implied.) In one embodiment, the filecomprises binary value assignments for those symbolic variables declaredby $esp_var.

[0039] After performing symbolic simulation, the process performsdetermines whether any error PLI (i.e., $esp_error) was executed(processing block 103). If no error PLI was executed, the process ends.If an error PLI was executed, the process generates a file, referred toherein as “esp_testvector”, which includes the variable assignments(processing block 104). Then, based on the contents of the file, theprocess replays or uses a binary simulator environment to handle anyfaults.

[0040] An Exemplary Application

[0041] An exemplary circuit is shown in FIG. 3. Considering thetestbench required to run the simulation, the following is given: moduletest_bench( ); reg [15:0] A, B, O32; reg CI; reg [3:0] INST; wire CO;reg [31:0] a,b reg [3:0] i; wire [15:0] out; DUT ALU(A,B,INST,CLK,out,CO); initial begin  $esp_var (a,b,i);  A = a[15:0];  B= b[15:0];  CI = 1′b0;  INST = i; # cycle  O32 [15:0] = out;  A = a[31:16];  B = b [31:16];  CI = CO; # cycle  O32 [31:16] = out  if ((INST= = 4′b0100) & ({CO, O32} !== (a+b))) // addition checking  begin  $display(“ALU ERROR: addition error is detected”);  $esp_error(“Binary vector is created for error detection”);  end endendmodule

[0042] In the case of the ALU, it is possible to run one symbolic testvector sweep and fully verify the block. The $esp_var command instructsthe simulator to interpret the variables as symbolic and, using a seriesof assert statements, the user can verify the functionality for everypossible combination of input values. Additionally, there are a set ofdebugging commands, $display( ) and $esp_error( ), that will help trackand eliminate bugs that symbolic simulation has highlighted.

[0043] Because of the use of the added commands, an individual does nothave to spend any time deciding a set of input values, symbolic vectorscover every and all possible combinations. So, if no bugs are detected,the tester can have confidence that there is no combination of valuesthat will cause an error to occur.

[0044] In one embodiment, all of the inputs are not treatedsymbolically. This may be the result of too little or unacceptablememory usage. The user may be allowed to select which inputs require theuse symbols. In an alternative embodiment, the testing engine randomlyselects symbols. The selection may be based on ensuring that thesimulation finishes. The user is notified of which signals wereassociated with symbols.

[0045] In one embodiment, the simulator accepts Verilog behavior, RTL,gate and transistor level inputs and works with most standard PLIroutines. In one embodiment, a SPICE netlist is converted to a Verilogswitch level netlist. In such a case, the symbolic simulator runssymbolic simulation on the transistor level netlist and compares theresults with and RTL description. Thus, if using self-checking orreference models in Verilog, there is very little change required to usesymbolic simulation.

[0046] Whereas many alterations and modifications of the presentinvention will no doubt become apparent to a person of ordinary skill inthe art after having read the foregoing description, it is to beunderstood that any particular embodiment shown and described by way ofillustration is in no way intended to be considered limiting. Therefore,references to details of various embodiments are not intended to limitthe scope of the claims which in themselves recite only those featuresregarded as essential to the invention.

[0047] Thus, a method and apparatus for improved design verification hasbeen described.

I claim:
 1. A method for performing design verification, the methodcomprising: specifying at least one object that represents at least onesignal as a symbol in a design using a first programming interface call(PLI) command; and instructing a symbolic simulator with the firstcommand to treat the at least one object as a symbol.
 2. The methoddefined in claim 1 further comprising: inserting the first command intoa design specification; and inputting the design specification into thesymbolic simulator.
 3. The method defined in claim 1 wherein the atleast one object comprise a hardware description language object.
 4. Themethod defined in claim 1 wherein the at least one object comprises aVerilog object.
 5. The method defined in claim 1 wherein the firstcommand comprises a Programming Language Interface (PLI).
 6. The methoddefined in claim 1 wherein the at least one signal comprises an input.7. The method defined in claim 1 further comprising: specifying a checkusing a second command, the check to perform a test to validate designfunctionality; and instructing the symbolic simulator using the secondcommand to perform the test.
 8. The method defined in claim 7 furthercomprising: inserting the first and second commands into a designspecification; and inputting the design specification into the symbolicsimulator.
 9. The method defined in claim 7 wherein the second commandcomprises a PLI.
 10. The method defined in claim 7 further comprising:instructing the symbolic simulator to generate a file with informationto locate an identified fault.
 11. An article of manufacture having atleast one recordable medium having stored thereon executableinstructions which, when executed by at least one processing device,cause the at least one processing device to: specify at least one objectthat represents at least one signal as a symbol in a design using afirst command; and instruct a symbolic simulator with the first commandto treat the at least one object as a symbol.
 12. The article ofmanufacture defined in claim 11 further comprising executableinstructions stored on the at least one recordable medium which, whenexecuted by at least one processing device, cause the at least oneprocessing device to: insert the first command into a designspecification; and input the design specification into the symbolicsimulator.
 13. The article of manufacture defined in claim 11 whereinthe at least one object comprise a hardware description language object.14. The article of manufacture defined in claim 11 wherein the at leastone object comprises a Verilog object.
 15. The article of manufacturedefined in claim 11 wherein the first command comprises a ProgrammingLanguage Interface (PLI).
 16. The article of manufacture defined inclaim 11 wherein the at least one signal comprises an input.
 17. Thearticle of manufacture defined in claim 11 further comprising executableinstructions stored on the at least one recordable medium which, whenexecuted by at least one processing device, cause the at least oneprocessing device to: specify a check using a second command, the checkto perform a test to validate design functionality; and instruct thesymbolic simulator using the second command to perform the test.
 18. Thearticle of manufacture defined in claim 17 further comprising executableinstructions stored on the at least one recordable medium which, whenexecuted by at least one processing device, cause the at least oneprocessing device to: insert the first and second commands into a designspecification; and input the design specification into the symbolicsimulator.
 19. The article of manufacture defined in claim 17 whereinthe second command comprises a PLI.
 20. The article of manufacturedefined in claim 17 further comprising executable instructions stored onthe at least one recordable medium which, when executed by at least oneprocessing device, cause the at least one processing device to: instructthe symbolic simulator to generate a file with information to locate anidentified fault.